FETs, particularly those fabricated from compound semiconductors such as Gallium Arsenide (“GaAs”), make very good signal amplification devices for RF and microwave applications. Chief among these are large-signal (or power) amplifier circuits. The FET's combination of high maximum frequency of oscillation, high current handling capability, high breakdown voltage and good linearity make these devices very attractive for such applications. Unfortunately, conventional FET devices have a relatively large size and therefore a relatively high manufacturing cost. Die size for a FET may be driven by at least two factors: (1) The requirement for many wide source and drain fingers in the active area of the device to support the large gate periphery, and (2) the large outboard bonding pads.
With regard to a standard FET, current flows between the source and the drain and the amount of current flowing is controlled by the voltage applied to the gate. Typically the source and drain fingers are approximately 25 microns each in width and the channel in which the gate is positioned is approximately five microns in width.
One major yield driver for a typical power FET device includes breaks in the gate fingers which may be no more than a few gate lengths (the small dimension, typically 0.25-0.5 microns) in size. Because the gate is only fed from one end, any break would leave the gate finger beyond the discontinuity unconnected from its voltage source and, therefore, unable to control the current flowing in that section of the channel. This effectively renders the device inoperable.
For example, suppose a power FET device has 50 gate fingers each two millimeters in width, giving a total gate periphery of 100 mm (a typical value for such a device). It will be assumed that the probability of any single one millimeter segment of gate finger (Y0) not having a break in it is 99.9%, a typical fabrication yield for such devices. The probability of there not being a break in any one entire two millimeter gate finger would be Yf=Y0^2=99.8%. Therefore, the probability of no breaks in any one of the 50 gate fingers is Yt=Yf^50=90.5%. So the overall device yield in the case where all the gate fingers are fed from one end is about 90%.
What is needed is an improved FET device that can be utilized in RF and microwave circuits that remedy the aforementioned deficiencies and create circuits that have relatively smaller die size, higher manufacturing yield, and greater reliability relative to common RF and microwave circuits.